Heretofore, in a semiconductor integrated circuit device, a silicon oxide film that is an insulator is provided over an integrated circuit formed in a semiconductor substrate, and wiring layers are disposed on the silicon oxide film for wiring respective elements composing the integrated circuit under the silicon oxide film to each other and bonding pads for connecting to external electrodes. For the purpose of reducing chip area, it has been generally known to pass wiring layers such as metallic wirings of aluminum or bonding pads over the respective elements, especially over a collector region. However, between a wiring layer passing, for example, over a collector region and that collector region, there is formed a parasitic capacitor using the silicon oxide film as a dielectric material, especially in a high frequency amplifier circuit or the like, and this results in undesired local feed-back through this parasitic capacitor, causing abnormal oscillation, deterioration in performance, etc. Such troubles cannot be foreseen at the stage of design, so that cut and try must be repeated until such troubles are eliminated, which prolongs the time required for design of a semiconductor integrated circuit device. Therefore, in general, in order to prevent the troubles caused by parasitic capacitors, it has been the practice to avoid overlapping between a wiring layer and an element which is liable to form the parasitic capacitor in question. However, according to this method a wiring layer is compelled to make a detour, resulting in an increase in chip area, and this in turn raises the cost of the semiconductor integrated circuit devices. In addition, an increase of resistance due to the increased length of the wiring layer causes additional troubles such as degradation of performance.